After the Due arrived the following transmitter was designed and implemented.
The data flow is as follows.
- Read uint10 value from an analog input.
- Normalize values to 4 bit (it was determined from testing that anything more than 4 bits and the sampling rate used the Due couldn’t process fast enough)
- Convert data to a [4:1] vector, one row per bit
- Read out the data from these two vectors
- Interlace these two outputs such that the output form the 1 sample switch is A0 B0 A1 B1 and so on
This job lies upon the “Integer to Bit” converter block.
Above is the current implementation of the transmitter. The most important part of this whole setup is how to actually convert the data properly into the desired format.
As mentioned the output of the “Integer to Bit” block is a 4 by 1 vector which requires the “index vector block to access each individual bit in order. However in order to properly interlace the bits in a regular and alternating order the counters and clock was used.
Both counters are essentially identical allowing us to index through each vector from 0 to 3 using the clock to trigger the count up. However the only difference between these two counters is when they trigger. Using the rising edge for one and the falling edge for the other allows one to use one clock cycle for two purposes..
Finally the 1 sample switch using a reset switch triggers every rising edge clock cycle allowing us to essentially interlace these two outputs.