Regular Paging

• Starting with the 80386 processor all x86 processors use 4kB pages

Linear Address Format (32 Bits) 3 fields

• Directory: Most Significant 19 bits
• Table: Middle 10 bits
• Offset: Least significant 12 bitss

Two Level Translation Scheme

• This is done in order to reduce the amount of RAM required for preprocess page tables
  1. First the address of the page table is loaded from the page directory table using the directory bits
  2. Then the correct table is chosen from the table bits
  3. Finally the offset is added in order to obtain the correct physical address
• Using a one level paging scheme would mean allowing all 2^20 possible entries occupy the page table eating all the RAM.
  • Two Level paging allows only required pages to be allocated thus saving memory
• The actual process looks like the image below.  Note the cr3 register contains the physical address of the page directory

• If each piece of data is one byte then there are 4096 bytes of data per page

Structure of Page Directories and Page Tables (same)

• Present flag: If 1 the page is in main memory otherwise it is on disk. If the entry of a Page Table or Page Directory needed to perform an address translation has the Present flag 0, the paging unit stores the linear address in a control register cr2 and generates exception 14: the Page Fault exception.
• Twenty MSB of page frame physical address: The base address of a page frame or table.
• Access flag: Set everytime paging unit accesses page frame only cleared by OS never by the paging unit itself.  This flag may be used by the operating system when selecting pages to be swapped out.
• Dirty flag: Same as above but only applies when a write occurs. 
• Read/write flag: Access rights two types
• User/supervisor flag: Mark what privilege is required in order to access the data
• PCD and PWT flag: Controls how the data is handled by the hardware cache
  • Setting PCD disables caching
• Page size flag: Applies only to page directories if set refers to page frame of size 2mb or  4mb (discussed later, 2mb for PAE 4mb for no PAE)
• Global flag: Applies only to Page Table entries. Prevent frequently used pages from being flushed from the TLB cache (Translation Lookaside Buffers (TLB)). It works only if the Page Global Enable (PGE) flag of register cr4  is set. (discussed later)