The Physical Page Extension (PAE) Paging Mechanism 

  • 32 bits allow for theoretically up to 4Gb of RAM however due to linear address space requirements only about 1Gb can actually be used  (discussed later)
  • This was solved by increasing the amount of pins for the memory bus from 32 to 36 in addition to this they added PAE to take advantage of the new space alerting
    • 4*2^4=64gb of RAM now
    • 32 linear address bits address 36 physical address bits
  • Enabled by setting the PAE flag in tune cr4 register PS flag in page directory now sets 2mb page frame 
  • 4 address pins added to processors 32->36

Format of PAE

  • 64 GB of RAM are split into 2^24 distinct page frames
    • Physical address field of Page Table entries has been expanded from 20 to 24 bits.
    • PAE Page Table entry must include the 12 flag bits (section “Regular Paging”) , 24 physical address bits, for a grand total of 36
    • Page Table entry size has been doubled from 32 bits to 64 bits.
      • 4-KB PAE Page Table includes 512 entries instead of 1,024
  • Added one more level of paging using the Page Directory Pointer Table (PDPT)
    • This is a table with 4, 64 bit entries 
  • cr3 now contains the 27 bit base address for the PDPT and not the page directory
    • PDPTs are stored in the first 4 GB of RAM and aligned to
      a multiple of 32 bytes (2^
      5), 27 bits are sufficient to represent the base address of such tables (?)

Linear Address Format Using PAE for 4kb Pages

  • cr3: Points to PDPT
  • bits 31-30: 1 of 4 possible entries in PDPT
  • bits 29-21: 1 of 512 possible entries in the page directory
  • bits 20-12: 1 of 512 possible entries in the page table
  • bits 11-0: offset on 4kb page

 

File:X86 Paging PAE 4K.svg

for 4 kb pages

 

Linear Address Format Using PAE for 2mB Pages

  • cr3: points to PDPT
  • bits 31-30: 1 of 4 possible entries in PDPT
  • bits 29-21: 1 of 512 possible entries in page directory
  • bits 20-0: offset to 2mb page
File:X86 Paging PAE 2M.svg

for a 2mb page

Limitations of PAE

  • It is important to note that linear addresses still remain at 32 bits therefore the actual linear address space remained the same size why we enlarged the physical address space
    • Therefore linear addresses will be reused when mapping to different parts of RAM
    • This is only a hack allowing one to use 32 bits to address 64 GB of RAM

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