
- 32 bit arch
- 2 paging levels (no PAE)
- Doesn’t use Page Upper Directory and Page Middle Directory initialized to all 0s
- Keep in mind base address is retained for Page Uppder/Middle Directories to make sure the code can execute on 64 bit systems without crashing
- This is done by setting both tables to have one entry only and mapping them to the Page Global Directory as usual
- 3 paging levels (using PAE)
- Page Global directory ==PDPT (Page Directory Pointer Table)
- Page Upper directory not used
- Page Middle directory ==Page Directory
- Page Table remains the same
- 2 paging levels (no PAE)
- 64 bit arch
- 4 paging levels
- Page Global Directory->Page Upper Directory->Page Middle Directory->Page Table
- 4 paging levels
- Each process has its own Page Global Directory and Page Tables
- When switching processes cr3 is loaded with the correct address of the Page Global Directory of the new process so proper memory reads may be performed
Why 4 level scheme for 64 bit?
- Each process gets private physical address space protecting against addressing errors
- Distinguish pages (groups of data) from page frames (physical addresses in main memory)
- Allows for a page of data stored in a page frame to be saved to disk and reloaded into another page frame (allows for virtual memory (ch17?))
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