The Linear Address Fields

For more detailed descriptions please refer to the book.

• Macros Used for Page Table Handling
  • PAGE_SHIFT
    • Length of offset field 12 bits for 4kb pages
  • PMD_SHIFT
    • Log of size of area Page Middle Directory maps to
    • Length of offset+table field of linear address 12+10=22 bits for PAE off
    • PAE on 12+9=21 bits
  • PMD_SIZE
    • Size mapped by single entry in Page Middle Directory
  • PMD_MASK
    • Mask offset and table fields of a linear address
    • 0xffc00000 PAE disabled
    • 0xffe00000 PAE enabled
  • LARGE_PAGE_SIZE
    • For when system uses large pages (2 levels of paging to 1 level)
    • Size of a large page=PMD_SIZE=2*PMD_SHIFT
  • LARGE_PAGE_MASK
    • Same as normal mask except is for more bits
  • PUD_SHIFT (always equal to PMD_SHIFT)
    • Log of size of area Page Upper Directory entry maps to
    • Should be 10 bits (?)
  • PUD_SIZE (always 2 or 4mb (2^10*1^12=middle dir*offset))
    • Size of area mapped by single entry in Page Upper Directory
  • PGDIR_SHIFT
    • Log of size of area Page Global Directory entry maps to
    • 22 for PAE disabled and 2 level paging 10 bits for Page Table and 12 for offset (4mB)
    • 30 for PAE enabled and 3 level paging 9 from Page Table 9 from Middle Page Table 12 from offset (1gB)
  • PGDIR_SIZE
    • Size of memory mapped to by a Page Global Directory entry
  • PGDIR_MASK
    • 0xffc00000 PAE Disabled
    • 0xc0000000 PAE Enabled
  • PTRS_PER_PTE, PTRS_PER_PMD, PTRS_PER_PUD, and PTRS_PER_PGD
    • Compute the number of entries in the Page Table, Page Middle Directory, Page Upper Directory, and Page Global Directory. They yield the values 1,024, 1, 1, and 1,024, respectively, when PAE is disabled; and the values 512, 512, 1, and 4, respectively, when PAE is enabled.
      • Recall halved due to the extra level of paging of the PDPT