Translation Lookaside Buffers (TLB)

• TLB: Another cache used to speed up linear->physical address translation
• Each CPU has its own TLB and TLBs do not need to be synced
  • This is because each CPU may associate different linear addresses with different physical ones]
• Changing the cr3 register (page directory base address) will invalidate all TLB entries

Usage

• When a linear address is first accessed it gets translated into a physical address (through paging as discussed before)
• Afterwards it is stored into the TLB such that further accesses will pull the physical address from the TLB instead of computing it again