Process Page Tables

  • Linear addresses are divided into 2 sections
    1. User/Kernel Mode: These addresses can both be allotted to processes in user or kernel  mode. They range from 0x00000000 to 0xbfffffff
      • Kernel may need to access User Mode linear addresses to retrive or store data
    2. Kernel Only Mode: These addresses can only be allotted to processes in kernel mode.  They range from 0xc0000000 to 0xffffffff
  • PAGE_OFFSET macro has value 0xc0000000 and is used as an offset into kernel linear address space

 

  • The first entries of the Page Global Directory map linear addresses lower than 0xc0000000
    • For PAE disabled. 768 4Mb pages (768*4 = ~ 3GB using 3:1 User Kernel ratio)
      • A page table entry requires 32 bits, so 1024 of them (covering 4MB of virtual address space) can be stored in one page. If the virtual address space is 3GB (as it is on many x86 systems), 768 pages would be required to hold all of the page table entries.
    • For PAE enabled. 3 Entries (PDPT). Only 3 because 3:1 User to Kernel ratio
      • All three levels of page tables are present. The page global directory (PGD) contains only four entries, each corresponding to 1GB of virtual address space; the PGD is indexed using the top two bits of the virtual address.

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